The present invention relates to semiconductor devices, and more specifically, to fin-type field effect transistor (FET) devices.
As the desire to reduce semiconductor scaling continues, planar-type semiconductor devices have been replaced with fin-type semiconductor devices, which are typically referred to as fin-type field effect transistor devices, or “finFETs.” Unlike planar-type FETs which include a gate that contacts only an upper surface of the channel, FinFET devices include one or more gates that wrap around the sidewalls and upper surface of the channel region. The increased gate-contact area improves electrical control over the channel region thereby overcoming various short-channel effects such as reducing leakage current, for example.
FinFET devices, however, are susceptible to high parasitic effects compared to conventional planar FETs. For instance, the source region and drain region of the finFET typically generate a different parasitic resistance and/or a different parasitic capacitance with respect to one another. Conventional solutions have attempted to compensate for variations in parasitic resistance and/or parasitic capacitance by adjusting the dimensions of the drain region with respect to the source region. These variations in source/drain dimensions have conventionally been achieved by implementing additional masking techniques in the finFET fabrication process flow. For example, additional masks are typically employed in the fabrication process flow to block source side when forming drain junction or vice versa. However, as the scaling of finFET devices and the pitch between gate structures continue to decrease, conventional masking techniques no longer effectively form the source/drain regions.